Traditionally, high temperature C4 (Controlled Collapse Chip Connection) bumps have been used to bond a chip to a substrate with the most common and widely utilized package being an organic laminate. Conventionally, the C4 bumps (solder bumps) are made from leaded solder, as it has superior properties. For example, lead is known to mitigate thermal coefficient (TCE) mismatch between the chip and the substrate (i.e., organic laminate). Accordingly, stresses imposed during the cooling cycle are mitigated by the C4 bumps, thus preventing delaminations or other damage from occurring to the chip or the substrate.
Lead-free requirements are now being imposed by many countries forcing manufacturers to implement new ways to produce chip to substrate joints. For example, solder interconnects consisting of tin/copper, tin/silver (with high concentrations of silver) and tin/gold in combination with SAC alloys are being used as a replacement for the leaded solder interconnects. With lead-free requirements, though, concerns about defects in C4 interconnections have surfaced, e.g., cracks in chip metallurgy under C4 bumps (named “white bumps” due to their appearance in C-Mode Scanning Acoustic Microscopy (CSAM) inspection processes) which lead to failure of the device. More specifically, white bumps are C4's that do not make good electrical contact to the Cu last metal pad, resulting in either failing chips at functional test or in the field. This may be attributable, at least in part, due to chip designs using high stress Pb-free C4 (solder bumps) which exacerbate C4/AlCu bump to Cu wire adhesion problems. Adhesion problems may also arise due to water absorption or fluorine instability in the fluorine-doped SiO2 (FSG) intermetal dielectric surface, either in damascene trenches (e.g. TaN liner/FSG interface) or on the planer FSG surface (FSG/SiN or FSG/SiCN interface).
As one illustrative example, during the chip joining reflow, the chip and its substrate are heated to an elevated temperature (about 250° C.) in order to form the solder interconnection joints. The initial portion of the cool down leads to little stress build up; however, as the joints solidify (around 180° C. for small lead-free joints), increased stress is observed on the package. In particular, as the package (laminate, solder and chip) begins to cool, the solder begins to solidify (e.g., at about 375° C.) and the laminate begins to shrink as the chip remains substantially the same size. The difference in thermal expansion between the chip and the substrate is accommodated by out-of-plane deformation (warpage) of the device and the substrate, and by the shear deformation of the solder joints. The peak stresses on the device occur during the cool down portion of the reflow.
As the solder is robust and exceeds the strength of the chip, tensile stresses begin to delaminate structures on the chip. The high shear stresses caused by the TCE mismatch between the chip (3.5 ppm) and the laminate (16 ppm) results in an interfacial failure (i.e., a separation between the BEOL copper and the dielectric (FSG) under the C4). This interfacial failure embodies itself as cracks in the chip metallurgy under C4 bumps.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.